1. Field of the Invention
The present disclosure pertains to the field of data processing systems. More particularly, the present disclosure pertains to levelizing transfer delays for multiple data transfer devices such as memory devices configured in a memory channel.
2. Description of Related Art
In some data transfer systems, data transfer delays between a set of system devices and a bus controller may need to be levelized, meaning that the data transfer delay is adjusted so that the sum of the data transfer delay and the propagation delay is equal to the same number of bus cycles for all devices on the bus. With levelized delays, the bus controller can respond to the entire set of system devices in a uniform manner. Such levelization is typically performed at system start-up or during another initialization period when data transfer to the set of devices is otherwise suspended. An efficient technique for levelizing delays may advantageously reduce the length of the initialization period, thereby allowing faster resumption or commencement of system processing activities.
Many prior art memory subsystems require an entire set of memory devices to respond during a single bus cycle. Although the response time may be programmed to a different value or extended by inserting wait states, all data is expected to arrive at the memory controller within the same clock cycle. A system in which all devices respond during the same clock cycle may not require delay levelization; however, such designs may require expensive printed circuit boards and may be limited in achievable bandwidth.
On the other hand, some systems include devices which are positioned along a relatively lengthy bus or "channel" such that the system does not attempt to complete data transmission along the bus during a single bus clock cycle. In fact, the clock rate for the bus may be high enough that devices on one end of the bus distant from the bus controller may have a several bus clock cycle propagation delay to the bus controller. Compounding the propagation delay problem, various devices along the channel may have different transaction response times.
A Rambus (TM) Direct Rambus Dynamic Random Access Memory (Direct RDRAM) bus is one example of a bus which utilizes memory devices along a channel. It is known that a Direct RDRAM Memory Controller (RMC) may expect to receive data from all devices along a channel during a particular bus cycle. In fact, a controller, described in "Direct RMC.d1 Data Sheet" available from Rambus Corporation of Mountain View, Calif., provides a controller delay register to assist in levelizing delays.
Additionally, one or more delay registers may also be provided within individual RDRAM devices (e.g., a T.sub.RDLY register discussed in the Rambus "Direct RDRAM 64/72-Mbit" Data Sheet at p. 36). Values may be stored in these registers in order to equalize delays between the various devices along the channel. Typically, the controller delay value is initialized first, then the delay values for individual memory devices are adjusted.
The prior art may not provide a mechanism to reduce the number of cycles performed during initialization. In general, the prior art may not specify particular ways to test only a subset of the total number of possible delay values. The prior art also may not specify a method of choosing initial values for certain delay testing iterations, an efficient order for testing delay values, a method for performing each test, or a way of aborting delay testing and disabling devices when certain values are reached. Thus, the prior art may not provide an adequate method for levelizing delays along a channel of devices.